Metal-oxide-semiconductor field-effect transistor (MOSFET) scaling has been accelerated because of the MOSFET's excellent performance and scaling properties. However, as the size of the MOSFET is reduced down to a deep submicron region, it suffers from some critical problems. One such problem is the increase of the subthreshold swing, which indicates how effectively a MOSFET can be turned OFF as gate voltage is decreased below a threshold voltage. Even with a theoretically perfect MOSFET, the subthreshold swing is approximately 60 mV/decade at room temperature. However, in actuality imperfections in MOSFET devices such as the presence of interface states or a nonzero value of gate oxide thickness result in the subthreshold swing being greater than 60 mV/decade at room temperature. Moreover, as the MOSFET device scales down to the deep submicron regime, the subthreshold swing increases rapidly due to substrate doping concentration increase. Consequently, the subthreshold swing of a typical submicron MOSFETs tends to be roughly 100 mV/decade at room temperature. Thus, conventional MOSFET scaling is limited by the subthreshold swing barrier that cannot be lower than 60 mV/decade.
The concept of I-MOS devices were proposed to overcome the subthreshold swing limit by utilizing modulation of the avalanche breakdown voltage of a gated p-i-n structure to control output current. Since the p-n junction barrier lowering is not the mechanism of current flow control in the device, it can reduce the subthreshold swing to less than 60 mV/decade at room temperature. In particular, it has been demonstrated that a subthreshold swing of 5.5 mV/decade can be achieved in an I-MOS device. However, it can be extremely challenging to form I-MOS devices with small dimensions with a tight pitch.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.